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MC68HC705JJ7 Datasheet, PDF (153/164 Pages) Freescale Semiconductor, Inc – Microcontrollers
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15.14 SIOP Timing (VDD = 5.0 Vdc)
Characteristic(1)
Symbol
Min
Frequency of operation
Master
Slave
fSIOP(M)
fSIOP(S)
0.25 x fOP
dc
Cycle time
Master
Slave
Clock (SCK) low time (fOP = 4.2 MHz)
SDO data valid time
SDO hold time
SDI setup time
SDI hold time
tSCK(M)
tSCK(M)
tSCKL
tV
tHO
tS
tH
4.0 x tcyc
—
952
—
0
100
100
1. +4.5 ≤ VDD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
SIOP Timing (VDD = 5.0 Vdc)
Typ
Max
0.25 x fOP
—
0.25 x fOP
1050
4.0 x tcyc
—
—
—
—
—
—
4.0 x tcyc
3.8
—
200
—
—
—
Unit
kHz
µs
ns
ns
ns
ns
ns
tSCK
tSCKL
SCK
tV
tHO
SDO
MSB
SDI
MSB
BIT 1
tS
VALID DATA
tH
LSB
LSB
Figure 15-11. SIOP Timing Diagram
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
153
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