MC68HC705JJ7 Datasheet, PDF (39/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Core Timer Interrupts
Therefore, the lowest power is consumed when OM1 is cleared. The state with both OM1 and OM2
set is provided so that the EPO can be started and allowed to stabilize while the LPO still clocks the
MCU. The reset state is for OM1 to be cleared and OM2 to be set, which selects the LPO and disables
the EPO.
IRQF — External Interrupt Request Flag
The IRQ flag is a clearable, read-only bit that is set when an external interrupt request is pending.
Writing to the IRQF bit has no effect. Reset clears the IRQF bit.
1 = Interrupt request pending
0 = No interrupt request pending
The following conditions set the IRQ flag:
• An external interrupt signal on the IRQ/V_PP pin
• An external interrupt signal on pin PA0, PA1, PA2, or PA3
when the PA0–PA3 pins are enabled by the PIRQ bit in the MOR to serve as external interrupt
sources.
The following conditions clear the IRQ flag:
• When the CPU fetches the interrupt vector
• When a logic 1 is written to the IRQR bit
IRQR — Interrupt Request Reset Bit
This write-only bit clears the IRQF flag bit and prevents redundant execution of interrupt routines.
Writing a logic 1 to IRQR clears the IRQF. Writing a logic 0 to IRQR has no effect. IRQR always reads
as a logic 0. Reset has no effect on IRQR.
1 = Clear IRQF flag bit
0 = No effect
4.6 Core Timer Interrupts
The core timer can generate the following interrupts:
• Timer overflow interrupt
• Real-time interrupt
Setting the I bit in the condition code register disables core timer interrupts. The controls and flags for
these interrupts are in the core timer status and control register (CTSCR) located at $0008.
4.6.1 Core Timer Overflow Interrupt
An overflow interrupt request occurs if the core timer overflow flag (TOF) becomes set while the core timer
overflow interrupt enable bit (TOFE) is also set. The TOF flag bit can be reset by writing a logic 1 to the
CTOFR bit in the CTSCR or by a reset of the device.
4.6.2 Real-Time Interrupt
A real-time interrupt request occurs if the real-time interrupt flag (RTIF) in the CTSCR becomes set while
the real-time interrupt enable bit (RTIE) is also set. The RTIF flag bit can be reset by writing a logical 1 to
the RTIFR bit in the CTSCR or by a reset of the device.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
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