MC68HC705JJ7 Datasheet, PDF (102/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Core Timer
10.2 Core Timer Status and Control Register
The read/write core timer status and control register (CTSCR) contains the interrupt flag bits, interrupt
enable bits, interrupt flag bit resets, and the rate selects for the real-time interrupt as shown in Figure 10-2.
Address: $0008
Bit 7
6
5
4
3
2
1
Bit 0
Read: CTOF
RTIF
0
0
CTOFE RTIE
RT1
RT0
Write:
CTOFR RTIFR
Reset:
0
0
0
0
0
0
1
1
= Unimplemented
Figure 10-2. Core Timer Status and Control Register (CTSCR)
CTOF — Core Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the core timer counter roll over from $FF
to $00. The CTOF flag bit generates a timer overflow interrupt request if CTOFE is also set. The CTOF
flag bit is cleared by writing a logic 1 to the CTOFR bit. Writing to CTOF has no effect. Reset clears
CTOF.
1 = Overflow in core timer has occurred.
0 = No overflow of core timer since CTOF last cleared
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected real-time interrupt (RTI) output becomes active.
RTIF generates a real-time interrupt request if RTIE is also set. The RTIF enable bit is cleared by
writing a logic 1 to the RTIFR bit. Writing to RTIF has no effect. Reset clears RTIF.
1 = Overflow in real-time counter has occurred.
0 = No overflow of real-time counter since RTIF last cleared
CTOFE — Core Timer Overflow Interrupt Enable Bit
This read/write bit enables core timer overflow interrupts. Reset clears CTOFE.
1 = Core timer overflow interrupts enabled
0 = Core timer overflow interrupts disabled
RTIE — Real-Time Interrupt Enable Bit
This read/write bit enables real-time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
CTOFR — Core Timer Overflow Flag Reset Bit
Writing a logic 1 to this write-only bit clears the CTOF bit. CTOFR always reads as a logic 0. Reset
does not affect CTOFR.
1 = Clear CTOF flag bit
0 = No effect on CTOF flag bit
RTIFR — Real-Time Interrupt Flag Reset Bit
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR always reads as a logic 0. Reset does
not affect RTIFR.
1 = Clear RTIF flag bit
0 = No effect on RTIF flag bit
RT1 and RT0 — Real-Time Interrupt Select Bits 1 and 0
These read/write bits select one of four real-time interrupt rates, as shown in Table 10-1. Because the
selected RTI output drives the COP watchdog, changing the real -time interrupt rate also changes the
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
102
Freescale Semiconductor