MC68HC705JJ7 Datasheet, PDF (112/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Programmable Timer
Table 11-1. Output Compare Initialization Example
9B
SEI
DISABLE INTERRUPTS
...
...
.....
...
...
.....
B7
16
STA
OCRH INHIBIT OUTPUT COMPARE
B6
13
LDA
TSR
ARM OCF FLAG FOR CLEARING
BF
17
STX
OCRL READY FOR NEXT COMPARE, OCF CLEARED
...
...
.....
...
...
.....
9A
CLI
ENABLE INTERRUPTS
11.6 Timer Control Register
The timer control register (TCR) shown in Figure 11-10, performs the following functions:
• Enables input capture interrupts
• Enables output compare interrupts
• Enables timer overflow interrupts
• Controls the active edge polarity of the TCAP signal
• Controls the active level of the TCMP output
Reset clears all the bits in the TCR with the exception of the IEDG bit which is unaffected.
Address:
Read:
Write:
Reset:
$0012
Bit 7
ICIE
0
6
5
OCIE
TOIE
0
0
= Unimplemented
4
3
2
0
0
0
0
0
0
U = Unaffected
1
IEDG
U
Bit 0
OLVL
0
Figure 11-10. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on the TCAP pin or from CPF2 flag
bit of the analog subsystem voltage comparator 2. Reset clears the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable Bit
This read/write bit enables interrupts caused by an active match of the output compare function. Reset
clears the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables interrupts caused by a timer overflow. Reset clears the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
112
Freescale Semiconductor