MC68HC705JJ7 Datasheet, PDF (57/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port A
PDICL — Lower Port C Pulldown Inhibit Bits (MC68HC705JP7)
Writing to this write-only bit controls the port C pulldown devices on the lower four bits (PC0–PC3).
Reading these pulldown register A bits returns undefined data. Reset clears bit PDICL.
1 = Lower four port C pins pulldown devices turned off
0 = Lower four port C pins pulldown devices turned on if pin has been programmed by the DDRC
to be an input
PDIA5–PDIA0 — Port A Pulldown Inhibit Bits
Writing to these write-only bits controls the port A pulldown devices. Reading these pulldown register
A bits returns undefined data. Reset clears bits PDIA5–PDIA0.
1 = Corresponding port A pin pulldown device turned off
0 = Corresponding port A pin pulldown device turned on if pin has been programmed by the DDRA
to be an input
7.2.4 Port A External Interrupts
The PIRQ bit in the MOR enables the PA3–PA0 pins to serve as external interrupt pins in addition to the
IRQ/V_PP pin. The active interrupt state for the PA3–PA0 pins is a logic 1 or a rising edge. A state of the
PIRQ bit in the MOR determines whether external interrupt inputs are edge-sensitive only or both edge-
and level-sensitive. Port A interrupts are also interactive with each other and the IRQ/V_PP pin as described
in 4.5 External Interrupts.
NOTE
When testing for external interrupts, the BIH and BIL instructions test the
voltage on the IRQ/V_PP pin, not the state of the internal IRQ signal.
Therefore, BIH and BIL cannot test the port A external interrupt pins.
7.2.5 Port A Logic
When a PA0:PA5 pin is programmed as an output, reading the port bit actually reads the value of the data
latch and not the voltage on the pin itself. When a PA0:PA5 pin is programmed as an input, reading the
port bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of
its DDR bit. Figure 7-4 shows the I/O logic of PA0–PA5 pins of port A.
The data latch can always be written, regardless of the state of its DDR bits. Table 7-1 summarizes the
operations of the port A pins.
Table 7-1. Port A Pin Functions
Port A
Pin(s)
PA0
PA1
PA2
PA3
PA4
PA5
SWPDI
(in MOR)
0
0
1
X⁽²⁾
Port A
PDIAx
DDRAx⁽¹⁾
0
0
1
0
X
0
X⁽²⁾
1
PORTA Access
(Pin or Data Register)
Read
Write
Pin
Data
Pin
Data
Pin
Data
Data
Data
Result on
Port A Pins
Pulldown
Pin
On
PAx in
Off
PAx in
Off
PAx in
Off
PAx out
1. DDRA can always be read or written.
2. Don’t care
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
57