MC68HC705JJ7 Datasheet, PDF (121/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

EPROM Registers
DELAY — Stop Startup Delay Bit
This EPROM bit selects the number of bus cycles that must elapse before bus activity begins following
a restart from the stop mode.
1 = Startup delay is 4064 bus cycles.
0 = Startup delay is 16 bus cycles.
CAUTION
The 16-cycle delay option will work properly in devices with the internal
low-power oscillator or with a steady external clock source. Check
crystal/ceramic resonator specifications carefully before using the 16-cycle
delay option with a crystal or ceramic resonator.
OSCRES — Oscillator Resistor Bit
This EPROM bit configures the internal shunt resistor.
1 = Oscillator configured with 2 M¾ shunt resistor
0 = Oscillator configured without a shunt resistor
NOTE
The optional oscillator resistor is NOT recommended for devices that use
an external RC oscillator. For such devices, this bit should be left erased as
a 0.
SWAIT — STOP Conversion to WAIT Bit
This EPROM bit disables the STOP instruction and prevents inadvertently turning off the COP
watchdog with a STOP instruction. When the SWAIT bit is set, a STOP instruction puts the MCU in
halt mode. Halt mode is a wait-like low-power state. The internal oscillator and timer clock continue to
run, but the CPU clock stops. When the SWAIT bit is clear, a STOP instruction stops the internal
oscillator, the internal clock, the CPU clock, the timer clock, and the COP watchdog timer.
1 = STOP instruction converted to WAIT instruction
0 = STOP instruction not converted to WAIT instruction
LVREN — Low-Voltage Reset Enable Bit
This EPROM bit enables the low-voltage reset (LVR) function.
1 = LVR function enabled
0 = LVR function disabled
PIRQ — Port A IRQ Enable Bit
This EPROM bit enables the PA3–PA0 pins to function as external interrupt sources.
1 = PA3–PA0 enabled as external interrupt sources
0 = PA3–PA0 not enabled as external interrupt sources
LEVEL — External Interrupt Sensitivity Bit
This EPROM bit makes the external interrupt inputs level-triggered as well as edge-triggered
1 = IRQ/V_PP pin negative-edge triggered and low-level triggered;
PA3–PA0 pins positive-edge triggered and high-level triggered
0 = IRQ/V_PP pin negative-edge triggered only; PA3–PA0 pins positive-edge triggered only
COPEN — COP Watchdog Enable Bit
This EPROM bit enables the COP watchdog.
1 = COP watchdog enabled
0 = COP watchdog disabled
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
121