MC68HC705JJ7 Datasheet, PDF (77/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog Control Register
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
CHG
ATD2
ATD1
ICEN
CPIE CP2EN CP1EN ISEN
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 8-5. Analog Control Register (ACR)
CHG
The CHG enable bit allows direct control of the charge current source and the discharge device and
also reflects the state of the discharge device. This bit is cleared by a reset of the device.
1 = If the ISEN bit is also set, the charge current source is sourcing current out of the PB0/AN0 pin.
Writing a logic 1 enables the charging current out of the PB0/AN0 pin.
0 = The discharge device is sinking current into the PB0/AN0 pin. Writing a logic 0 disables the
charging current and enables the discharging current into the PB0/AN0 pin, if the ISEN bit is
also set.
ATD1–ATD2
The ATD1–ATD2 enable bits select one of the four operating modes used for making A/D conversions
via the single-slope method.These four modes are given in Table 8-3. These bits have no effect if the
ISEN enable bit is cleared. These bits are cleared by a reset of the device and thereby return the
analog subsystem to the manual A/D conversion method.
Table 8-3. A/D Conversion Options
A/D
Option
Mode
Disabled
3
Charge
Control
Current
source and
discharge
disabled
Automatic
charge and
discharge
(OCF–ICF)
synchronized
to timer
A/D Options
ISEN ATD2 ATD1
0
X
X
1
0
0
1
1
0
1
1
1
1
1
1
CHG
Current Flow
to/from PB0/AN0
X
Current control disabled,
no source or sink current
Begin sourcing current
when the CHG bit is set
1 and continue to source
current until the CHG bit is
cleared.
The CHG bit remains set
1 until the next time ICF
occurs.
The CHG bit remains
0 cleared until the next time
OCF occurs.
The CHG bit remains set
1 until the next time ICF
occurs.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
77