MC68HC705JJ7 Datasheet, PDF (37/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

IRQ/V_PP
PA3
PA2
PA1
PA0
V_DD
IRQ
LATCH
R
RST
IRQ VECTOR FETCH
External Interrupts
V_PP TO
USER EPROM
AND PEPROM
TO BIH & BIL
INSTRUCTION
PROCESSING
EXTERNAL
INTERRUPT
REQUEST
MASK OPTION REGISTER ($1FF1)
INTERNAL DATA BUS
IRQ STATUS/CONTROL REGISTER ($000D)
Figure 4-3. External Interrupt Logic
4.5.2 PA0–PA3 Pins
Programming the PIRQ bit in the MOR to a logic 1 enables the PA0–PA3 pins (PA0:3) to serve as
additional external interrupt sources. A rising edge on a PA0:3 pin latches an external interrupt request.
After completing the current instruction, the CPU tests the IRQ latch. If the IRQ latch is set, the CPU then
tests the I bit in the condition code register and the IRQE bit in the ISCR. If the I bit is clear and the IRQE
bit is set, the CPU then begins the interrupt sequence. The CPU clears the IRQ latch while it fetches the
interrupt vector, so that another external interrupt request can be latched during the interrupt service
routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new
interrupt request.
The PA0:3 pins can be edge-triggered or edge- and level-triggered. External interrupt triggering sensitivity
is selected by the LEVEL bit in the MOR.
With the edge- and level-sensitive trigger MOR option, a rising edge or a high level on a PA0:3 pin latches
an external interrupt request. The edge- and level-sensitive trigger MOR option allows connection to a
PA0:3 pin of multiple wired-OR interrupt sources. As long as any source is holding the pin high, an
external interrupt request is present, and the CPU continues to execute the interrupt service routine.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
37