MC68HC705JJ7 Datasheet, PDF (64/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Parallel Input/Output
7.3.8 PB6/SDI Logic
The PB6/SDI pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as
shown in Figure 7-11. The operations of PB6/SDI pin are summarized in Table 7-3.
READ $0005
SERIAL DATA IN (SDI)
SERIAL ENABLE (SPE)
WRITE $0005
DATA DIRECTION
REGISTER B
BIT DDRB6
R
WRITE $0001
PORT B DATA
REGISTER
BIT PB6
PB6
SDI
READ $0001
WRITE $0011
RESET
PULLDOWN
REGISTER B
R
BIT PDIB6
MASK OPTION REG. ($1FF1)
PULLDOWN
DEVICE
Figure 7-11. PB6/SDI Pin I/O Circuit
When using the PB6/SDI pin, these interactions must be noted:
1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB6/SDI
pin buffer to be disabled to allow the PB6/SDI pin to act as an input that feeds the serial data input
(SDI) of the SIOP. The pulldown device is disabled in this case.
2. If the SIOP function is in control of the PB6/SDI pin, the DDRB6 and PB6 data register bits are still
accessible to the CPU and can be altered or read without affecting the SIOP functionality.
However, if the DDRB6 bit is cleared, reading the PB6 data register will return the current state of
the PB6/SDI pin.
3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored
in the DDRB6, PDIB6, and PB6 register bits will then control the PB6/SDI pin.
4. If the PB6/SDI pin is to be a digital input, then both the SPE bit in the SCR and the DDRB6 bit must
be cleared. Depending on the external application, the pulldown device may also be disabled by
setting the PDIB6 pulldown inhibit bit.
5. If the PB6/SDI pin is to be a digital output, then the SPE bit in the SCR must be cleared and the
DDRB6 bit must be set. The pulldown device will be disabled in this case.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
64
Freescale Semiconductor