MC68HC705JJ7 Datasheet, PDF (63/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port B
7.3.7 PB5/SDO Logic
The PB5/SDO pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as
shown in Figure 7-10. The operations of the PB5 pin are summarized in Table 7-3.
When using the PB5/SDO pin, these interactions must be noted:
1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB5/SDO
pin buffer to be enabled and to be driven by the serial data output (SDO) from the SIOP. The
pulldown device will be disabled in this case.
2. If the SIOP function is in control of the PB5/SDO pin, the DDRB5 and PB5 data register bits are
still accessible to the CPU and can be altered or read without affecting the SIOP functionality.
However, if the DDRB5 bit is cleared, reading the PB5 data register will return the current state of
the PB5/SDO pin.
SERIAL DATA OUT (SDO)
SERIAL ENABLE (SPE)
V_DD
READ $0005
WRITE $0005
DATA DIRECTION
REGISTER B
R
BIT DDRB5
WRITE $0001
PORT B DATA
REGISTER
BIT PB5
PB5
SDO
READ $0001
WRITE $0011
RESET
PULLDOWN
REGISTER B
R
BIT PDIB5
MASK OPTION REG. ($1FF1)
PULLDOWN
DEVICE
Figure 7-10. PB5/SDO Pin I/O Circuit
3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored
in the DDRB5, PDIB5, and PB5 register bits will then control the PB5/SDO pin.
4. If the PB5/SDO pin is to be a digital input, then both the SPE bit in the SCR and the DDRB5 bit
must be cleared. Depending on the external application, the pulldown device may also be disabled
by setting the PDIB5 pulldown inhibit bit.
5. If the PB5/SDO pin is to be a digital output, then the SPE bit in the SCR must be cleared and the
PDIB5 bit must be set. The pulldown device will be disabled in this case.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
63