MC68HC705JJ7 Datasheet, PDF (55/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7
Parallel Input/Output
7.1 Introduction
The MC68HC705JJ7 has 14 bidirectional input/output (I/O) pins which form two parallel I/O ports, A
and B. The MC68HC705JP7 has 22 bidirectional I/O pins which form three parallel I/O ports, A, B and C.
Each I/O pin is programmable as an input or an output. The contents of the data direction registers
determine the data direction of each of the I/O pins. All I/O pins have software programmable pulldown
devices which can be enabled or disabled globally by the SWPDI bit in the mask option register (MOR).
7.2 Port A
Port A is a 6-bit, general-purpose, bidirectional I/O port with these features:
• Individual programmable pulldown devices
• High current sinking capability on all port A pins, with a maximum total for port A
• High current sourcing capability on all port A pins, with a maximum total for port A
• External interrupt capability (pins PA3–PA0)
7.2.1 Port A Data Register
The port A data register (PORTA) contains a bit for each of the port A pins. When a port A pin is
programmed to be an output, the state of its data register bit determines the state of the output pin. When
a port A pin is programmed to be an input, reading the port A data register returns the logic state of the
pin. The upper two bits of the port A data register will always read as logic 0s.
Address:
Read:
Write:
Reset:
Alternate:
$0000
Bit 7
6
5
4
3
2
1
0
0
PA5
PA4
PA3
PA2
PA1
Unaffected by reset
= Unimplemented
KYBD3 KYBD2 KYBD1
Figure 7-1. Port A Data Register (PORTA)
Bit 0
PA0
KYBD0
PA5–PA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of each bit is under the control of the
corresponding bit in the port A data direction register (DDRA). Reset has no effect on port A data.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
55