MC68HC705JJ7 Datasheet, PDF (111/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Output Compare Registers
R/W
OCRH
$FFFC
OCRH ($0016)
OCRL ($0017)
16-BIT COMPARATOR
16-BIT COUNTER
OUTPUT COMPARE
(OCF)
R/W
OCRL
EDGE
SELECT
DETECT
LOGIC
PB4
AN4
TCMP
INTERNAL
÷4
CLOCK
(OSC ÷ 2)
TIMER
INTERRUPT
REQUEST
RESET
TIMER CONTROL REG.
$0012
TIMER STATUS REG.
$0013
Figure 11-8. Timer Output Compare Block Diagram
INTERNAL
DATA
BUS
Address: $0016
Bit 7
6
Read:
Bit 15
14
Write:
Reset:
5
4
3
2
13
12
11
10
Unaffected by reset
1
Bit 0
9
Bit 8
Address: $0017
Bit 7
6
Read:
Bit 7
6
Write:
Reset:
5
4
3
2
5
4
3
2
Unaffected by reset
1
Bit 0
1
Bit 0
Figure 11-9. Output Compare Registers (OCRH and OCRL)
Writing to the OCRH before writing to the OCRL inhibits timer compares until the OCRL is written.
Reading or writing to the OCRL after reading the TCR will clear the output compare flag bit (OCF). The
output compare OLVL state will be clocked to its output latch regardless of the state of the OCF.
To prevent OCF from being set between the time it is read and the time the output compare registers are
updated, use this procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is written.
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This also clears the OCF flag bit in
the TSR.
5. Enable interrupts by clearing the I bit in the condition code register.
A software example of this procedure is shown in Table 11-1.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
111