MC68HC705JJ7 Datasheet, PDF (104/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Core Timer
periodically by a program sequence. Writing a logic 0 to COPC bit in the COPR register clears the COP
watchdog and prevents a COP reset.
Address: $1FF0
Bit 7
6
5
4
3
2
Read:
OPT
Write: EPMSEC
Reset:
Unaffected by reset
= Unimplemented
1
Bit 0
COPC
Figure 10-4. COP and Security Register (COPR)
EPMSEC — EPROM Security^{((1)) Bit}
The EPMSEC bit is a write-only security bit to protect the contents of the user EPROM code stored in
locations $0700–$1FFF.
OPT — Optional Features Bit
The OPT bit enables two additional features: direct drive by comparator outputs to port A and voltage
offset capability to sample capacitor in analog subsystem.
1 = Optional features enabled
0 = Optional features disabled
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. The COP watchdog is active in the run, wait, and halt
modes of operation if the COP is enabled by setting the COPEN bit in the MOR. The STOP instruction
disables the COP watchdog by clearing the counter and turning off its clock source.
In applications that depend on the COP watchdog, the STOP instruction can be disabled by setting the
SWAIT bit in the MOR. In applications that have wait cycles longer than the COP timeout period, the
COP watchdog can be disabled by clearing the COPEN bit. Table 10-2 summarizes recommended
conditions for enabling and disabling the COP watchdog.
NOTE
If the voltage on the IRQ/V_PP pin exceeds 1.5 × V_DD, the COP watchdog
turns off and remains off until the IRQ/V_PP pin voltage falls below
1.5 × V_DD.
Table 10-2. COP Watchdog Recommendations
Voltage on
IRQ/V_PP Pin
Less than 1.5 × V_DD
SWAIT
(in MOR)⁽¹⁾
1
Wait/Halt Time
Less than COP
timeout period
Recommended COP
Watchdog Condition
Enabled⁽²⁾
Less than 1.5 × V_DD
1
Greater than COP
timeout period
Disabled
Less than 1.5 × V_DD
0
X⁽³⁾
More than 1.5 × V_DD
X
X⁽³⁾
Disabled
Disabled
1. The SWAIT bit in the MOR converts STOP instructions to HALT instructions.
2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction.
3. Don’t care
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM
difficult for unauthorized users.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
104
Freescale Semiconductor