MC68HC705JJ7 Datasheet, PDF (103/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Core Timer Counter Register
counting rate of the COP watchdog. Reset sets RT1 and RT0, selecting the longest COP timeout
period and longest real-time interrupt period.
NOTE
Changing RT1 and RT0 when a COP timeout is imminent or uncertain may
cause a real-time interrupt request to be missed or an additional real-time
interrupt request to be generated. Clear the COP timer just before changing
RT1 and RT0.
Table 10-1. Core Timer Interrupt Rates and COP Timeout Selection
Timer Overflow
Interrupt Period
TOF = 1/(f_OSC ÷ 2¹¹)
(Microseconds)
@ f_OSC (MHz)
4.2 2.0 1.0
MHz MHz MHz
RT1 RT0
RTI
Rate
= f_OSC
divided
by:
00
2¹⁵
01
2¹⁶
488 1024 2048
10
2¹⁷
11
2¹⁸
Real-Time
Interrupt Period
(RTI)
(Milliseconds)
@ f_OSC (MHz)
4.2 2.0 1.0
MHz MHz MHz
7.80 16.4 32.8
15.6 32.8 65.5
31.2 65.5 131
62.4 131 262
COP Timeout Period
COP = 7-to-8 RTI Periods
(Milliseconds)
4.2 MHz
Min Max
54.6 62.4
109 125
218 250
437 499
@ f_OSC (MHz)
2.0 MHz
Min Max
115 131
229 262
459 524
918 1049
1.0 MHz
Min Max
229 262
459 524
918 1049
1835 2097
10.3 Core Timer Counter Register
A 15-stage ripple counter driven by a divide-by-eight prescaler is the basis of the core timer. The value of
the first eight stages is readable at any time from the read-only timer counter register as shown in
Figure 10-3.
Address: $0009
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-3. Core Timer Counter Register (CTCR)
Power-on clears the entire counter chain and begins clocking the counter. After the startup delay (16 or
4064 internal bus cycles depending on the DELAY bit in the mask option register (MOR)), the power-on
reset circuit is released, clearing the counter again and allowing the MCU to come out of reset.
Each count of the timer counter register takes eight oscillator cycles or four cycles of the internal bus. A
timer overflow function at the eighth counter stage allows a timer interrupt every 2048 oscillator clock
cycles or every 1024 internal bus cycles.
10.4 COP Watchdog
Four counter stages at the end of the core timer make up the computer operating properly (COP)
watchdog which can be enabled by the COPEN bit in the MOR. The COP watchdog is a software error
detection system that automatically times out and resets the MCU if the COP watchdog is not cleared
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
103