MC68HC705JJ7 Datasheet, PDF (68/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Parallel Input/Output
7.4.3 Port C Pulldown Devices
All port C pins can have software programmable pulldown devices enabled or disabled globally by the
SWPDI bit in the MOR. These pulldown devices are individually controlled by the write-only pulldown
register A (PDRA) shown in Figure 7-3. PDICH controls the upper four pins (PC7–PC4) and PDICL
controls the lower four pins (PC3–PC0). Clearing the PDICH or PDICL bits in the PDRA turns on the
pulldown devices if the port C pin is an input. Reading the PDRA returns undefined results since it is a
write-only register. Reset clears the PDICH and PDICL bits, which turns on all the port C pulldown
devices.
7.4.4 Port C Logic
Figure 7-15 shows the I/O logic of port C.
When a port C pin is programmed as an output, reading the port bit actually reads the value of the data
latch and not the voltage on the pin itself. When a port C pin is programmed as an input, reading the port
bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its
DDR bit. Table 7-4 summarizes the operations of the port C pins.
READ $0006
WRITE $0006
WRITE $0002
READ $0002
WRITE $0010
RESET
DATA DIRECTION
REGISTER C
R
BIT DDRCx
PORT C DATA
REGISTER
BIT PCx
PULLDOWN
REGISTER A
BIT PDICx
R
MASK OPTION REGISTER ($1FF1)
Figure 7-15. Port C I/O Circuit
PCx
HIGH SINK/SOURCE
CURRENT CAPABILITY
PULLDOWN
DEVICE
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
68
Freescale Semiconductor