MC68HC705JJ7 Datasheet, PDF(75/164 Page) Freescale Semiconductor, Inc

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MC68HC705JJ7 Datasheet, PDF (75/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Analog Multiplex Register

RISE

V+

WHEN

V+ > Vâ

V+

RISE

WHEN

V+ > Vâ

VIO +

COMP

VIO +

COMP

Vâ

INV = 0

INV = 1

Figure 8-4. INV Bit Action

NOTE

Either comparator may generate an output flag when the inputs are

exchanged due to a change in the state of the INV bit. It is therefore

recommended that the INV bit not be changed while waiting for a

comparator flag. Further, any changes to the state of the INV bit should be

followed by writing a logic 1 to both the CPFR1 and CPFR2 bits to clear any

extraneous CPF1 or CPF2 flags that may have occurred.

VREF

This read/write bit connects the channel select bus to VDD for making a reference voltage

measurement. It cannot be selected if any of the other input sources to the channel select bus are

selected as shown in Table 8-2. This bit is cleared by a reset of the device.

1 = Channel select bus connected to VDD if all MUX1:4 are cleared.

0 = Channel select bus cannot be connected to VDD.

MUX1:4

These are read/write bits that connect the analog subsystem pins to the channel select bus and voltage

comparator 2 for purposes of making a voltage measurement. They can be selected individually or

combined with any of the other input sources to the channel select bus as shown in Table 8-2.

NOTE

The VAOFF voltage source shown in Figure 8-1 depicts a small offset

voltage generated by the total chip current passing through the package

bond wires and lead frame that are attached to the single VSS pin. This

offset raises the internal VSS reference (AVSS) in the analog subsystem

with respect to the external VSS pin. Turning on the VSS MUX to the channel

select bus connects it to this internal AVSS reference line.

When making A/D conversions, this AVSS offset gets placed on the external

ramping capacitor since the discharge device on the PB0/AN0 pin

discharges the external capacitor to the internal AVSS line. Under these

circumstances, the positive input (+) to comparator 2 will always be higher

than the negative input (â) until the negative input reaches the AVSS offset

voltage plus any offset in comparator 2.

MC68HC705JJ7 â¢ MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1

Freescale Semiconductor

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