MC68HC705JJ7 Datasheet, PDF (19/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

IRQ/V_PP Pin
1.8 IRQ/V_PP Pin
The IRQ/V_PP input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt
function uses the LEVEL bit in the MOR to provide either negative edge-sensitive triggering or both
negative edge-sensitive and low level-sensitive triggering. If the LEVEL bit is set to enable level-sensitive
triggering, the IRQ/V_PP pin requires an external resistor to V_DD for “wired-OR” operation. If the IRQ/V_PP
pin is not used, it must be tied to the V_DD supply. The IRQ/V_PP pin contains an internal Schmitt trigger as
part of its input to improve noise immunity.
The voltage on this pin may affect operation if the voltage on the IRQ/V_PP pin is above V_DD when the
device is released from a reset condition. The IRQ/V_PP pin should only be taken above V_DD to program
an EPROM memory location or personality EPROM bit. For more information, refer to 15.13 PEPROM
and EPROM Programming Characteristics.
NOTE
Each of the PA0–PA3 I/O pins may be connected as an OR function with
the IRQ interrupt function by the PIRQ bit in the MOR. This capability allows
keyboard scan applications where the transitions or levels on the I/O pins
will behave the same as the IRQ/V_PP pin, except that active transitions and
levels are inverted. The edge or level sensitivity selected by the LEVEL bit
in the MOR for the IRQ/V_PP pin also applies to the I/O pins that are ORed
to create the IRQ signal. For more information, refer to 4.5 External
Interrupts.
1.9 PA0–PA5
These six I/O lines comprise port A, a general-purpose bidirectional I/O port. This port also has four pins
which have keyboard interrupt capability. All six of these pins have high current source and sink capability.
All of these pins have software programmable pulldowns which can be disabled by the SWPDI bit in the
MOR.
1.10 PB0–PB7
These eight I/O lines comprise port B, a general-purpose bidirectional I/O port. This port is also shared
with the 16-bit programmable timer input capture and output compare functions, with the two voltage
comparators in the analog subsystem, and with the simple serial interface (SIOP).
The outputs of voltage comparator 1 can directly drive the PB4 pin; and the PB4 pin has high current
source and sink capability.
All of these pins have software programmable pulldowns which can be disabled by the SWPDI bit in the
MOR.
1.11 PC0–PC7 (MC68HC705JP7)
These eight I/O lines comprise port C, a general-purpose bidirectional I/O port. This port is only available
on the 28-pin MC68HC705JP7. All eight of these pins have high current source and sink capability.
All of these pins have software programmable pulldowns which can be disabled by the SWPDI bit in the
MOR.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
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