English
Language : 

MC68HC705JJ7 Datasheet, PDF (140/164 Pages) Freescale Semiconductor, Inc – Microcontrollers
◁
Electrical Specifications
15.5 Supply Current Characteristics (VDD = 4.5 to 5.5 Vdc)
Characteristic(1)
RUN(3) (analog and LVR disabled)
Internal low-power oscillator at 100 kHz
Internal low-power oscillator at 500 kHz
External oscillator running at 4.2 MHz
WAIT(4) (analog and LVR disabled)
Internal low-power oscillator at 100 kHz
Internal low-power oscillator at 500 kHz
External oscillator running at 4.2 MHz
STOP(5) (analog and LVR disabled)
Typical
–40°C to 85°C
Incremental IDD for enabled modules
LVR
Analog subsystem
Symbol
Min
IDD
—
—
—
IDD
—
—
—
IDD
—
—
IDD
—
—
Typ(2)
150
375
3.00
45
75
1.00
2
4
5
380
Max
Unit
568
µA
1100
µA
5.20
mA
85
µA
375
µA
2.20
mA
10
µA
20
15
µA
475
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25°C only
3. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all
inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait IDD is affected linearly by the OSC2 capacitance.
5. Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc, OSC1 = VDD.
15.6 Supply Current Characteristics (VDD = 2.7 to 3.3 Vdc)
Characteristic(1)
RUN(3) (analog and LVR disabled)
Internal low-power oscillator at 100 kHz
Internal low-power oscillator at 500 kHz
External oscillator running at 2.1 MHz
WAIT(4) (analog and LVR disabled)
Internal low-power oscillator at 100 kHz
Internal low-power oscillator at 500 kHz
External oscillator running at 2.1 MHz
STOP(5) (analog and LVR disabled)
25°C
–40°C to 85°C
Incremental IDD for enabled modules
LVR
Analog subsystem
Symbol
Min
IDD
—
—
—
IDD
—
—
—
IDD
—
—
IDD
—
—
Typ(2)
70
320
1.25
20
40
0.50
1
2
5
380
Max
Unit
320
µA
800
µA
2.60
mA
65
µA
250
µA
1.10
mA
5
µA
10
15
µA
475
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25°C only.
3. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all
inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait IDD is affected linearly by the OSC2 capacitance.
5. Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc, OSC1 = VDD.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
140
Freescale Semiconductor
 ▷