MC68HC705JJ7 Datasheet, PDF (74/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog Subsystem
Case
Hold
sample
voltage
Divide input
Direct input
Internal
temperature
diode
1. Don’t care
HOLD
(AMUX)
0
0
1
1
Table 8-1. Comparator 2 Input Sources
DHOLD
(AMUX)
0
1
0
1
OPT
(MOR)
0
1
1
X⁽¹⁾
X⁽¹⁾
X⁽¹⁾
VOFF
(ASR)
X⁽¹⁾
0
1
X⁽¹⁾
X⁽¹⁾
X⁽¹⁾
Voltage
Offset
No
Yes
No
No
No
Source To Negative Input
of Comparator 2
Sample capacitor connected to
comparator 2 negative input; very low leakage
current.
Sample capacitor connected to comparator 2
negative input; bottom of capacitor offset from V_SS
by approximately 100 mV, very low leakage current.
Signal on channel selection bus is divided
by 2 and connected to sample capacitor
and comparator 2 negative input
Signal on channel selection bus is connected
directly to sample capacitor and comparator 2
negative input.
Internal temperature sensing diode connected
directly to sample capacitor and comparator 2
negative input.
During a reset, the HOLD bit is set and the DHOLD bit is cleared, which connects the internal sample
capacitor to the channel selection bus. And since a reset also clears the MUX[1:4] bits, then the
channel selection bus will be connected to V_SS and the internal sample capacitor will be discharged to
V_SS following the reset.
NOTE
When sampling a voltage for later conversion, the HOLD and DHOLD bits
should be cleared before making any changes in the MUX channel
selection. If the MUX channel and the HOLD/DHOLD are changed on the
same write cycle to the AMUX register, the sampled voltage may be altered
during the channel switching.
INV
This is a read/write bit that controls the relative polarity of the inherent input offset voltage of the voltage
comparators. This bit allows voltage comparisons to be made with both polarities and then averaged
together by taking the sum of the two readings and then dividing by 2 (logical shift right).
The polarity of the input offset is reversed by interchanging the internal voltage comparator inputs while
also inverting the comparator output. This interchange does not alter the action of the voltage
comparator output with respect to its port pins. That is, the output will only go high if the voltage on the
positive input (PB2 pin for comparator 1 and PB0 pin for comparator 2) is above the voltage on the
respective negative input (PB3 pin for comparator 1 and PB1 pin for comparator 2). This is shown
schematically in Figure 8-4. This bit is cleared by a reset of the device.
1 = The voltage comparators are internally inverted.
0 = The voltage comparators are not internally inverted.
NOTE
The effect of changing the state of the INV bit is to only change the polarity
of the input offset voltage. It does not change the output phase of the CPF1
or CPF2 flags with respect to the external port pins.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
74
Freescale Semiconductor