MC9S08GB60 Datasheet, PDF (94/290 Pages) Motorola, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
PTGD
PTGPE
PTGSE
PTGDD
Bit 7
Read:
PTGD7
Write:
Reset: 0
6
PTGD6
0
5
PTGD5
0
4
PTGD4
0
3
PTGD3
0
2
PTGD2
0
1
PTGD1
0
Bit 0
PTGD0
0
Read:
PTGPE7 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0
Write:
Reset: 0
0
0
0
0
0
0
0
Read:
PTGSE7 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0
Write:
Reset: 0
0
0
0
0
0
0
0
Read:
PTGDD7 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 6-15. Port G Registers
PTGDn — Port PTG Data Register Bit n (n = 0–7)
For port G pins that are inputs, reads return the logic level on the pin. For port G pins that are
configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic
level is driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
PTGPEn — Pullup Enable for Port G Bit n (n = 0–7)
For port G pins that are inputs, these read/write control bits determine whether internal pullup devices
are enabled. For port G pins that are configured as outputs, these bits are ignored and the internal pullup
devices are disabled.
1 = Internal pullup device enabled.
0 = Internal pullup device disabled.
PTGSEn — Slew Rate Control Enable for Port G Bit n (n = 0–7)
For port G pins that are outputs, these read/write control bits determine whether the slew rate
controlled outputs are enabled. For port G pins that are configured as inputs, these bits are ignored.
1 = Slew rate control enabled.
0 = Slew rate control disabled.
MC9S08GB/GT Data Sheet, Rev. 2.3
94
Freescale Semiconductor