MC9S08GB60 Datasheet, PDF (118/290 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
7.5.1 ICG Control Register 1 (ICGC1)
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
RANGE REFS
0
CLKS
OSCSTEN 0⁽¹⁾
Reset: 0
1
0
0
0
1
0
0
= Unimplemented or Reserved
1. This bit is reserved for Freescale Semiconductor internal use only. Any write operations to this register should write
a 0 to this bit.
Figure 7-12. ICG Control Register 1 (ICGC1)
RANGE — Frequency Range Select
The RANGE bit controls the oscillator, reference divider, and FLL loop prescaler multiplication factor
(P). It selects one of two reference frequency ranges for the ICG. The RANGE bit is write-once after
a reset. The RANGE bit only has an effect in FLL engaged external and FLL bypassed external modes.
1 = Oscillator configured for high frequency range. FLL loop prescale factor P is 1.
0 = Oscillator configured for low frequency range. FLL loop prescale factor P is 64.
REFS — External Reference Select
The REFS bit controls the external reference clock source for ICGERCLK. The REFS bit is write-once
after a reset.
1 = Oscillator using crystal or resonator requested.
0 = External clock requested.
CLKS — Clock Mode Select
The CLKS bits control the clock mode according to Figure 7-13. If FLL bypassed external is
requested, it will not be selected until ERCS = 1. If the ICG enters off mode, the CLKS bits will remain
unchanged.Writes to the CLKS bits will not take effect if a previous write is not complete.
Figure 7-13. CLKS Clock Select
CLKS[1:0]
00
01
10
11
Clock Mode
Self-clocked
FLL engaged, internal reference
FLL bypassed, external reference
FLL engaged, external reference
The CLKS bits are writable at any time, unless the first write after a reset was CLKS = 0X, the CLKS bits
cannot be written to 1X until after the next reset (because the EXTAL pin was not reserved).
MC9S08GB/GT Data Sheet, Rev. 2.3
118
Freescale Semiconductor