MC9S08GB60 Datasheet, PDF (162/290 Pages) Motorola, Inc – Microcontrollers

Timer/PWM (TPM) Module
PS2:PS1:PS0 — Prescale Divisor Select
This 3-bit field selects one of eight divisors for the TPM clock input as shown in Table 10-2. This
prescaler is located after any clock source synchronization or clock source selection, so it affects
whatever clock source is selected to drive the TPM system.
Table 10-2. Prescale Divisor Selection
PS2:PS1:PS0
TPM Clock Source Divided-By
0:0:0
1
0:0:1
2
0:1:0
4
0:1:1
8
1:0:0
16
1:0:1
32
1:1:0
64
1:1:1
128
10.7.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The
coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMxCNTH or
TPMxCNTL, or any write to the timer status/control register (TPMxSC).
Reset clears the TPM counter registers.
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15
14
13
12
11
10
9
Bit 8
Write:
Any write to TPMxCNTH clears the 16-bit counter.
Reset: 0
0
0
0
0
0
0
0
Figure 10-6. Timer x Counter Register High (TPMxCNTH)
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
Any write to TPMxCNTL clears the 16-bit counter.
Reset: 0
0
0
0
0
0
0
0
Figure 10-7. Timer x Counter Register Low (TPMxCNTL)
MC9S08GB/GT Data Sheet, Rev. 2.3
162
Freescale Semiconductor