MC9S08GB60 Datasheet, PDF (69/290 Pages) Motorola, Inc – Microcontrollers

Reset, Interrupt, and System Control Registers and Control Bits
IRQPE — IRQ Pin Enable
This read/write control bit enables the IRQ pin function. When this bit is set, the IRQ pin can be used
as an interrupt request. Also, when this bit is set, either an internal pull-up or an internal pull-down
resistor is enabled depending on the state of the IRQMOD bit.
1 = IRQ pin function is enabled.
0 = IRQ pin function is disabled.
IRQF — IRQ Flag
This read-only status bit indicates when an interrupt request event has occurred.
1 = IRQ event detected.
0 = No IRQ request.
IRQACK — IRQ Acknowledge
This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF). Writing 0
has no meaning or effect. Reads always return 0. If edge-and-level detection is selected
(IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQIE — IRQ Interrupt Enable
This read/write control bit determines whether IRQ events generate a hardware interrupt request.
1 = Hardware interrupt requested whenever IRQF = 1.
0 = Hardware interrupt requests from IRQF disabled (use polling).
IRQMOD — IRQ Detection Mode
This read/write control bit selects either edge-only detection or edge-and-level detection. The
IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request
events. See Section 5.5.2.2, “Edge and Level Sensitivity” for more details.
1 = IRQ event on falling edges and low levels or on rising edges and high levels.
0 = IRQ event on falling edges or rising edges only.
5.8.2 System Reset Status Register (SRS)
This register includes six read-only status flags to indicate the source of the most recent reset. When a
debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be
set. Writing any value to this register address clears the COP watchdog timer without affecting the contents
of this register. The reset state of these bits depends on what caused the MCU to reset.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
69