MC9S08GB60 Datasheet, PDF (165/290 Pages) Motorola, Inc – Microcontrollers

TPM Registers and Control Bits
CPWMS
X
0
1
MSnB:MSnA
XX
00
01
1X
XX
Table 10-3. Mode, Edge, and Level Selection
ELSnB:ELSnA
Mode
Configuration
00
Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
01
Capture on rising edge only
10
Input capture Capture on falling edge only
11
Capture on rising or falling edge
00
Software compare only
01
Toggle output on compare
Output compare
10
Clear output on compare
11
Set output on compare
10
Edge-aligned ^{High-true pulses (clear output on compare)}
X1
PWM
Low-true pulses (set output on compare)
10
Center-aligned ^{High-true pulses (clear output on compare-up)}
X1
PWM
Low-true pulses (set output on compare-up)
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
ELSnB:ELSnA — Edge/Level Select Bits
Depending on the operating mode for the timer channel as set by CPWMS:MSnB:MSnA and shown
in Table 10-3, these bits select the polarity of the input edge that triggers an input capture event, select
the level that will be driven in response to an output compare match, or select the polarity of the PWM
output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated
to any timer channel functions. This function is typically used to temporarily disable an input capture
channel or to make the timer pin available as a general-purpose I/O pin when the associated timer
channel is set up as a software timer that does not require the use of a pin. This is also the setting
required for channel 0 when the TPMxCH0 pin is used as an external clock input.
10.7.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
165