MC9S08GB60 Datasheet, PDF (75/290 Pages) Motorola, Inc – Microcontrollers

Reset, Interrupt, and System Control Registers and Control Bits
LVDRE — Low-Voltage Detect Reset Enable
This read/write bit enables LVDF events to generate a hardware reset (provided LVDE = 1).
1 = Force an MCU reset when LVDF = 1.
0 = LVDF does not generate hardware resets.
LVDSE — Low-Voltage Detect Stop Enable
Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function operates
when the MCU is in stop mode.
1 = Low-voltage detect enabled during stop mode.
0 = Low-voltage detect disabled during stop mode.
LVDE — Low-Voltage Detect Enable
This read/write bit enables low-voltage detect logic and qualifies the operation of other bits in this
register.
1 = LVD logic enabled.
0 = LVD logic disabled.
5.8.8 System Power Management Status and Control 2 Register (SPMSC2)
This register is used to report the status of the low voltage warning function, and to configure the stop mode
behavior of the MCU.
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVWF
Write:
0
LVWACK
LVDV
LVWV
PPDF
0
PDC
PPDACK
PPDC
Power-on reset: 0¹
0
0
0
0
0
0
0
LVD reset: 0⁽¹⁾
0
U
U
0
0
0
0
Any other reset: 0⁽¹⁾
0
U
U
0
0
0
0
= Unimplemented or Reserved
U = Unaffected by reset
1 _{LVWF will be set in the case when VSupply transitions below the trip point or after reset and VSupply is already below}
V_LVW.
Figure 5-9. System Power Management Status and Control 2 Register (SPMSC2)
LVWF — Low-Voltage Warning Flag
The LVWF bit indicates the low-voltage warning status.
1 = Low voltage warning is present or was present.
0 = Low voltage warning not present.
LVWACK — Low-Voltage Warning Acknowledge
The LVWACK bit indicates the low-voltage warning acknowledge.
Writing a 1 to LVWACK clears LVWF to 0 if a low voltage warning is not present.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
75