MC9S08GB60 Datasheet, PDF (74/290 Pages) Motorola, Inc – Microcontrollers

Chapter 5 Resets, Interrupts, and System Configuration
Table 5-2. Real-Time Interrupt Period
RTIS2:RTIS1:RTIS0
Internal Clock Source ¹
(t_RTI = 1 ms, Nominal)
External Clock Source ²
Period = t_ext
0:0:0
Disable periodic wakeup timer
Disable periodic wakeup timer
0:0:1
8 ms
t_ext x 256
0:1:0
32 ms
t_ex x 1024
0:1:1
64 ms
t_ex x 2048
1:0:0
128 ms
t_ex x 4096
1:0:1
256 ms
t_ext x 8192
1:1:0
512 ms
t_ext x 16384
1:1:1
1.024 s
t_ex x 32768
1 _{See Table A-10 tRTI in Appendix A, “Electrical Characteristics” for the tolerance on these values.}
2 _{text is based on the external clock source, resonator, or crystal selected by the ICG configuration. See Table A-9 for details.}
5.8.7 System Power Management Status and Control 1 Register (SPMSC1)
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVDF
0
0
0
LVDIE LVDRE¹ LVDSE⁽¹⁾ LVDE⁽¹⁾
Write:
LVDACK
Reset: 0
0
0
1
1
1
0
0
= Unimplemented or Reserved
1 _{This bit can be written only one time after reset. Additional writes are ignored.}
Figure 5-8. System Power Management Status and Control 1 Register (SPMSC1)
LVDF — Low-Voltage Detect Flag
Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
LVDACK — Low-Voltage Detect Acknowledge
This write-only bit is used to acknowledge low voltage detection errors (write 1 to clear LVDF). Reads
always return 0.
LVDIE — Low-Voltage Detect Interrupt Enable
This read/write bit enables hardware interrupt requests for LVDF.
1 = Request a hardware interrupt when LVDF = 1.
0 = Hardware interrupt disabled (use polling).
MC9S08GB/GT Data Sheet, Rev. 2.3
74
Freescale Semiconductor