MC9S08GB60 Datasheet, PDF (254/290 Pages) Motorola, Inc – Microcontrollers

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15.5.3.7 Debug Control Register (DBGC)
This register can be read or written at any time.
Bit 7
6
5
4
3
2
1
Read:
DBGEN ARM
Write:
TAG BRKEN RWA RWAEN RWB
Reset: 0
0
0
0
0
0
0
Figure 15-7. Debug Control Register (DBGC)
DBGEN — Debug Module Enable
Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
1 = DBG enabled.
0 = DBG disabled.
Bit 0
RWBEN
0
ARM — Arm Control
Controls whether the debugger is comparing and storing information in the FIFO. A write is used to
set this bit (and the ARMF bit) and completion of a debug run automatically clears it. Any debug run
can be manually stopped by writing 0 to ARM or to DBGEN.
1 = Debugger armed.
0 = Debugger not armed.
TAG — Tag/Force Select
Controls whether break requests to the CPU will be tag or force type requests. If BRKEN = 0, this bit
has no meaning or effect.
1 = CPU breaks requested as tag type requests.
0 = CPU breaks requested as force type requests.
BRKEN — Break Enable
Controls whether a trigger event will generate a break request to the CPU. Trigger events can cause
information to be stored in the FIFO without generating a break request to the CPU. For an end trace,
CPU break requests are issued to the CPU when the comparator(s) and R/W meet the trigger
requirements. For a begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL
does not affect the timing of CPU break requests.
1 = Triggers cause a break request to the CPU.
0 = CPU break requests not enabled.
RWA — R/W Comparison Value for Comparator A
When RWAEN = 1, this bit determines whether a read or a write access qualifies comparator A. When
RWAEN = 0, RWA and the R/W signal do not affect comparator A.
1 = Comparator A can only match on a read cycle.
0 = Comparator A can only match on a write cycle.
MC9S08GB/GT Data Sheet, Rev. 2.3
254
Freescale Semiconductor