MC9S08GB60 Datasheet, PDF (136/290 Pages) Motorola, Inc – Microcontrollers

Central Processor Unit (CPU)
rel — Any label or expression that refers to an address that is within –128 to +127
locations from the next address after the last byte of object code for the current
instruction. The assembler will calculate the 8-bit signed offset and include it in
the object code for this instruction.
Address modes
INH =
IMM =
DIR =
EXT =
IX =
IX+ =
IX1 =
IX1+ =
IX2 =
REL =
SP1 =
SP2 =
Inherent (no operands)
8-bit or 16-bit immediate
8-bit direct
16-bit extended
16-bit indexed no offset
16-bit indexed no offset, post increment (CBEQ and MOV only)
16-bit indexed with 8-bit offset from H:X
16-bit indexed with 8-bit offset, post increment
(CBEQ only)
16-bit indexed with 16-bit offset from H:X
8-bit relative offset
Stack pointer with 8-bit offset
Stack pointer with 16-bit offset
Table 8-1. HCS08 Instruction Set Summary (Sheet 1 of 7)
Source
Form
Operation
Description
Effect
on CCR
VH I NZC
ADC #opr8i
ADC opr8a
ADC opr16a
ADC oprx16,X
ADC oprx8,X
ADC ,X
ADC oprx16,SP
ADC oprx8,SP
ADD #opr8i
ADD opr8a
ADD opr16a
ADD oprx16,X
ADD oprx8,X
ADD ,X
ADD oprx16,SP
ADD oprx8,SP
AIS #opr8i
AIX #opr8i
AND #opr8i
AND opr8a
AND opr16a
AND oprx16,X
AND oprx8,X
AND ,X
AND oprx16,SP
AND oprx8,SP
Add with Carry
Add without Carry
Add Immediate Value
(Signed) to Stack Pointer
Add Immediate Value
(Signed) to Index
Register (H:X)
Logical AND
A ← (A) + (M) + (C)
A ← (A) + (M)
SP ← (SP) + (M)
M is sign extended to a 16-bit value
H:X ← (H:X) + (M)
M is sign extended to a 16-bit value
A ← (A) & (M)
IMM
DIR
EXT
–
IX2
IX1
IX
SP2
SP1
IMM
DIR
EXT
–
IX2
IX1
IX
SP2
SP1
– – – – – – IMM
– – – – – – IMM
0––
IMM
DIR
EXT
–
IX2
IX1
IX
SP2
SP1
A9 ii
2
B9 dd
3
C9 hh ll 4
D9 ee ff 4
E9 ff
3
F9
3
9ED9 ee ff 5
9EE9 ff
4
AB ii
2
BB dd
3
CB hh ll 4
DB ee ff 4
EB ff
3
FB
3
9EDB ee ff 5
9EEB ff
4
A7 ii
2
AF ii
2
A4 ii
2
B4 dd
3
C4 hh ll 4
D4 ee ff 4
E4 ff
3
F4
3
9ED4 ee ff 5
9EE4 ff
4
MC9S08GB/GT Data Sheet, Rev. 2.3
136
Freescale Semiconductor