MC9S08GB60 Datasheet, PDF (92/290 Pages) Motorola, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
PTEDDn — Data Direction for Port E Bit n (n = 0–7)
These read/write bits control the direction of port E pins and what is read for PTED reads.
1 = Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
0 = Input (output driver disabled) and reads return the pin value.
6.6.6 Port F Registers (PTFD, PTFPE, PTFSE, and PTFDD)
Port F includes eight general-purpose I/O pins that are not shared with any peripheral module. Port F pins
used as general-purpose I/O pins are controlled by the port F data (PTFD), data direction (PTFDD), pullup
enable (PTFPE), and slew rate control (PTFSE) registers.
PTFD
PTFPE
PTFSE
PTFDD
Bit 7
Read:
PTFD7
Write:
Reset: 0
6
PTFD6
0
5
PTFD5
0
4
PTFD4
0
3
PTFD3
0
2
PTFD2
0
1
PTFD1
0
Bit 0
PTFD0
0
Read:
PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0
Write:
Reset: 0
0
0
0
0
0
0
0
Read:
PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0
Write:
Reset: 0
0
0
0
0
0
0
0
Read:
PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 6-14. Port F Registers
PTFDn — Port PTF Data Register Bit n (n = 0–7)
For port F pins that are inputs, reads return the logic level on the pin. For port F pins that are configured
as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic
level is driven out the corresponding MCU pin.
Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
MC9S08GB/GT Data Sheet, Rev. 2.3
92
Freescale Semiconductor