MC9S08GB60 Datasheet, PDF (117/290 Pages) Motorola, Inc – Microcontrollers

Initial conditions:
1) Clock supplied from ATE has 500 µs duty period
2) ICG configured for internal reference with 4 MHz bus
START TRIM PROCEDURE
ICGTRM = $80, n = 1
ICG Registers and Control Bits
MEASURE
INCOMING CLOCK WIDTH
(COUNT = # OF BUS CLOCKS / 4)
COUNT < EXPECTED = 500
(RUNNING TOO SLOW)
CASE ST.ATEMENT ^{COUNT = EXPECTED = 500}
ICGTRM =
ICGTRM - 128 / (2**n)
(DECREASING ICGTRM
INCREASES THE FREQUENCY)
COUNT > EXPECTED = 500
(RUNNING TOO FAST)
ICGTRM =
ICGTRM + 128 / (2**n)
(INCREASING ICGTRM
DECREASES THE FREQUENCY)
STORE ICGTRM VALUE
IN NON-VOLATILE
MEMORY
n = n+1
CONTINUE
YES
IS n > 8?
NO
Figure 7-11. Trim Procedure
In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing final
test with automated test equipment. A separate signal or message is provided to the MCU operating under
user provided software control. The MCU initiates a trim procedure as outlined in Figure 7-11 while the
tester supplies a precision reference signal.
If the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using
a reduction divisor (R) twice the final value. Once the trim procedure is complete, the reduction divisor
can be restored. This will prevent accidental overshoot of the maximum clock frequency.
7.5 ICG Registers and Control Bits
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all ICG registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
117