MC9S08GB60 Datasheet, PDF (109/290 Pages) Motorola, Inc – Microcontrollers

Functional Description
Table 7-3. ICG State Table
Actual Desired
Mode Mode
(CLKST) (CLKS)
Off
(XX)
Off
(XX)
FBE
(10)
SCM
(00)
FEI
SCM
(01)
(00)
FBE
(10)
FEE
(11)
FEI
FEI
(01)
(01)
FEE
(11)
FBE
FBE
(10)
(10)
FEE
(11)
Reference
Range Frequency
(f_REFERENCE)
X
0
X
0
X
f_ICGIRCLK/7⁽²⁾
0
f_ICGIRCLK/7⁽¹⁾
X
f_ICGIRCLK/7⁽¹⁾
X
f_ICGIRCLK/7⁽¹⁾
0
f_ICGIRCLK/7
X
f_ICGIRCLK/7
X
0
X
0
Comparison
Cycle Time
—
—
8/f_ICGIRCLK
8/f_ICGIRCLK
8/f_ICGIRCLK
8/f_ICGIRCLK
8/f_ICGIRCLK
8/f_ICGIRCLK
—
—
FEE
FEE
(11)
(11)
0
f_ICGERCLK
2/f_ICGERCLK
1
f_ICGERCLK
128/f_ICGERCLK
ICGOUT
0
Conditions⁽¹⁾
for
CLKS = CLKST
—
Reason
CLKS ≠
CLKST
—
0
—
ERCS = 0
ICGDCLK/R
Not switching from
FBE to SCM
—
ICGDCLK/R
—
DCOS = 0
ICGDCLK/R
ICGDCLK/R
ICGDCLK/R
—
—
DCOS = 1
ERCS = 0
DCOS = 0 or
ERCS = 0
—
ICGDCLK/R
—
ERCS = 0
ICGERCLK/R
ICGERCLK/R
ICGDCLK/R⁽³⁾
ICGDCLK/R⁽²⁾
ERCS = 1
—
ERCS = 1 and
DCOS = 1
ERCS = 1 and
DCOS = 1
—
LOCS = 1 &
ERCS = 1
—
—
1. CLKST will not update immediately after a write to CLKS. Several bus cycles are required before CLKST updates to the new
value.
2. The reference frequency has no effect on ICGOUT in SCM, but the reference frequency is still used in making the comparisons
that determine the DCOS bit
3. After initial LOCK; will be ICGDCLK/2R during initial locking process and while FLL is re-locking after the MFD bits are
changed.
7.3.9 Fixed Frequency Clock
The ICG provides a fixed frequency clock output, XCLK, for use by on-chip peripherals. This output is
equal to the internal bus clock, BUSCLK, in FBE mode. In FEE mode, XCLK is equal to ICGERCLK ÷ 2
when the following conditions are met:
• (P × N) ÷ R ≥ 4 where P is determined by RANGE (see Table 7-5), N and R are determined by
MFD and RFD, respectively (see Table 7-6).
• LOCK = 1.
If the above conditions are not true, then XCLK is equal to BUSCLK.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
109