MC9S08GB60 Datasheet, PDF (70/290 Pages) Motorola, Inc – Microcontrollers

Chapter 5 Resets, Interrupts, and System Configuration
Bit 7
6
5
4
3
2
1
Bit 0
Read: POR
PIN
COP ILOP
0
ICG
LVD
0
Write:
Writing any value to SIMRS address clears COP watchdog timer.
Power-on reset: 1
0
0
0
0
0
1
0
Low-voltage reset: U
0
0
0
0
0
1
0
Any other reset: 0
1
(1)
(1)
0
(1)
0
0
U = Unaffected by reset
1 _{Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits}
corresponding to sources that are not active at the time of reset will be cleared.
Figure 5-3. System Reset Status (SRS)
POR — Power-On Reset
Reset was caused by the power-on detection logic. Because the internal supply voltage was ramping
up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVD threshold.
1 = POR caused reset.
0 = Reset not caused by POR.
PIN — External Reset Pin
Reset was caused by an active-low level on the external reset pin.
1 = Reset came from external reset pin.
0 = Reset not caused by external reset pin.
COP — Computer Operating Properly (COP) Watchdog
Reset was caused by the COP watchdog timer timing out. This reset source may be blocked by
COPE = 0.
1 = Reset caused by COP timeout.
0 = Reset not caused by COP timeout.
ILOP — Illegal Opcode
Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP instruction
is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
1 = Reset caused by an illegal opcode.
0 = Reset not caused by an illegal opcode.
ICG — Internal Clock Generation Module Reset
Reset was caused by an ICG module reset.
1 = Reset caused by ICG module.
0 = Reset not caused by ICG module.
MC9S08GB/GT Data Sheet, Rev. 2.3
70
Freescale Semiconductor