|
MC9S08GB60 Datasheet, PDF (160/290 Pages) Motorola, Inc – Microcontrollers | |||
|
◁ |
Timer/PWM (TPM) Module
10.6.4 PWM End-of-Duty-Cycle Events
For channels that are conï¬gured for PWM operation, there are two possibilities:
⢠When the channel is conï¬gured for edge-aligned PWM, the channel ï¬ag is set when the timer
counter matches the channel value register that marks the end of the active duty cycle period.
⢠When the channel is conï¬gured for center-aligned PWM, the timer count matches the channel
value register twice during each PWM cycle. In this CPWM case, the channel ï¬ag is set at the start
and at the end of the active duty cycle, which are the times when the timer counter matches the
channel value register.
The ï¬ag is cleared by the 2-step sequence described in Section 10.6.1, âClearing Timer Interrupt Flags.â
10.7 TPM Registers and Control Bits
The TPM includes:
⢠An 8-bit status and control register (TPMxSC)
⢠A 16-bit counter (TPMxCNTH:TPMxCNTL)
⢠A 16-bit modulo register (TPMxMODH:TPMxMODL)
Each timer channel has:
⢠An 8-bit status and control register (TPMxCnSC)
⢠A 16-bit channel value register (TPMxCnVH:TPMxCnVL)
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all TPM registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header ï¬le is used to translate these names into the appropriate absolute
addresses.
Some MCU systems have more than one TPM, so register names include placeholder characters to identify
which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x,
channel n and TPM1C2SC is the status and control register for timer 1, channel 2.
10.7.1 Timer x Status and Control Register (TPMxSC)
TPMxSC contains the overï¬ow status ï¬ag and control bits that are used to conï¬gure the interrupt enable,
TPM conï¬guration, clock source, and prescale divisor. These controls relate to all channels within this
timer module.
Bit 7
6
5
4
3
2
1
Bit 0
Read: TOF
TOIE CPWMS CLKSB CLKSA PS2
PS1
PS0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-5. Timer x Status and Control Register (TPMxSC)
MC9S08GB/GT Data Sheet, Rev. 2.3
160
Freescale Semiconductor
|
▷ |