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MC9S08GB60 Datasheet, PDF (231/290 Pages) Motorola, Inc – Microcontrollers
ATD Registers and Control Bits
RES8 — ATD Resolution Select
This bit determines the resolution of the ATD converter, 8-bits or 10-bits. The ATD converter has the
accuracy of a 10-bit converter. However, if 8-bit compatibility is required, selecting 8-bit resolution
will map result data bits 9-2 onto ATD1RH bits 7-0.
The effect of the RES8 bit on the result is shown in Table 14-3.
1 = 8-bit resolution selected.
0 = 10-bit resolution selected.
SGN — Signed Result Select
This bit determines whether the result will be signed or unsigned data. Signed data is represented as
2’s complement data and is achieved by complementing the MSB of the result. Signed data mode can
be used only when the result is left justified (DJM = 0) and is not available for right-justified mode
(DJM = 1). When a signed result is selected, the range for conversions becomes –512 ($200) to 511
($1FF) for 10-bit resolution and –128 ($80) to 127 ($7F) for 8-bit resolution.
The effect of the SGN bit on the result is shown in Table 14-3.
1 = Left justified result data is signed.
0 = Left justified result data is unsigned.
Table 14-3. Available Result Data Formats
RES8 DJM SGN
Data Formats of Result
Analog Input
VREFH = VDDA, VREFL = VSSA
ATD1RH:ATD1RL
VDDA
1
0
0
8-bit : left justified : unsigned
$FF:$00
1
0
1
8-bit : left justified : signed
$7F:$00
1
1
X1
8-bit : left justified2 : unsigned
$FF:$00
0
0
0
10-bit : left justified : unsigned
$FF:$C0
0
0
1
10-bit : left justified : signed
$7F:$C0
0
1
X1
10-bit : right justified : unsigned
$03:$FF
1 The SGN bit is only effective when DJM = 0. When DJM = 1, SGN is ignored.
2 8-bit results are always in ATD1RH.
VSSA
$00:$00
$80:$00
$00:$00
$00:$00
$80:$00
$00:$00
PRS — Prescaler Rate Select
This field of bits determines the prescaled factor for the ATD conversion clock. Table 14-4 illustrates
the divide-by operation and the appropriate range of bus clock frequencies.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
231