MC9S08GB60 Datasheet, PDF (171/290 Pages) Motorola, Inc – Microcontrollers

INTERNAL BUS
M
1 × BAUD
RATE CLOCK
Transmitter Functional Description
(WRITE-ONLY)
SCID – Tx BUFFER
LOOPS
RSRC
11-BIT TRANSMIT SHIFT REGISTER
H876543210L
SHIFT DIRECTION
LOOP
CONTROL
TO RECEIVE
DATA IN
TO TxD1 PIN
T8
PE
PARITY
PT
GENERATION
ENABLE
TE
SBK
TXDIR
TRANSMIT CONTROL
SCI CONTROLS TxD1
TxD1 DIRECTION
TO TxD1
PIN LOGIC
TDRE
TIE
TC
TCIE
Figure 11-3. SCI Transmitter Block Diagram
Tx INTERRUPT
REQUEST
The transmitter is enabled by setting the TE bit in SCIxC2. This queues a preamble character that is one
full character frame of logic high. The transmitter then remains idle (TxD1 pin remains high) until data is
available in the transmit data buffer. Programs store data into the transmit data buffer by writing to the SCI
data register (SCIxD).
The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long
depending on the setting in the M control bit. For the remainder of this section, we will assume M = 0,
selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits,
and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in
the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the
transmit data register empty (TDRE) status flag is set to indicate another character may be written to the
transmit data buffer at SCIxD.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
171