MC9S08GB60 Datasheet, PDF (217/290 Pages) Motorola, Inc – Microcontrollers

Inter-Integrated Circuit (IIC) Module
SRW — Slave Read/Write
When addressed as a slave the SRW bit indicates the value of the R/W command bit of the calling
address sent to the master.
1 = Slave transmit, master reading from slave.
0 = Slave receive, master writing to slave.
IICIF — IIC Interrupt Flag
The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by writing a
one to it in the interrupt routine. One of the following events can set the IICIF bit:
• One byte transfer completes
• Match of slave address to calling address
• Arbitration lost
1 = Interrupt pending.
0 = No interrupt pending.
RXAK — Receive Acknowledge
When the RXAK bit is low, it indicates an acknowledge signal has been received after the completion
of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge
signal is detected.
1 = No acknowledge received.
0 = Acknowledge received.
13.5.5 IIC Data I/O Register (IIC1D)
Bit 7
6
5
4
3
2
Read:
Write:
DATA
Reset:
0
0
0
0
0
0
Figure 13-9. IIC Data I/O Register (IIC1D)
1
Bit 0
0
0
DATA — Data
In master transmit mode, when data is written to the IIC1D, a data transfer is initiated. The most
significant bit is sent first. In master receive mode, reading this register initiates receiving of the next
byte of data.
NOTE
When transitioning out of master receive mode, the IIC mode should be
switched before reading the IIC1D register to prevent an inadvertent
initiation of a master receive data transfer.
In slave mode, the same functions are available after an address match has occurred.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
217