MC9S08GB60 Datasheet, PDF (81/290 Pages) Motorola, Inc – Microcontrollers

6.3.4 Port D, TPM1 and TPM2
Pin Descriptions
Port D
Bit 7
6
5
4
3
2
1
Bit 0
MCU Pin:
PTD7/
TPM2CH4
PTD6/
TPM2CH3
PTD5/
TPM2CH2
PTD4/
TPM2CH1
PTD3/
TPM2CH0
PTD2/
TPM1CH2
PTD1/
TPM1CH1
PTD0/
TPM1CH0
Figure 6-5. Port D Pin Names
Port D is an 8-bit port shared with the two TPM modules, TPM1 and TPM2, and general-purpose I/O.
When the TPM1 or TPM2 modules are enabled in output compare or input capture modes of operation,
the pin direction will be controlled by the module function.
Port D pins are available as general-purpose I/O pins controlled by the port D data (PTDD), data direction
(PTDDD), pullup enable (PTDPE), and slew rate control (PTDSE) registers. Refer to Section 6.4, “Parallel
I/O Controls” for more information about general-purpose I/O control.
The TPM2 module can be configured to use PTD7–PTD3 as either input capture, output compare, PWM,
or external clock input pins (PTD3 only). Refer to Chapter 10, “Timer/PWM (TPM) Module” for more
information about using PTD7–PTD3 as timer pins.
The TPM1 module can be configured to use PTD2–PTD0 as either input capture, output compare, PWM,
or external clock input pins (PTD0 only). Refer to Chapter 10, “Timer/PWM (TPM) Module” for more
information about using PTD2–PTD0 as timer pins.
6.3.5 Port E, SCI1, and SPI
Port E
Bit 7
MCU Pin: PTE7
6
5
4
3
PTE6
PTE5/ PTE4/
SPSCK1 MOSI1
PTE3/
MISO1
Figure 6-6. Port E Pin Names
2
PTE2/
SS1
1
PTE1/
RxD1
Bit 0
PTE0/
TxD1
Port E is an 8-bit port shared with the SCI1 module, SPI1 module, and general-purpose I/O. When the SCI
or SPI modules are enabled, the pin direction will be controlled by the module function.
Port E pins are available as general-purpose I/O pins controlled by the port E data (PTED), data direction
(PTEDD), pullup enable (PTEPE), and slew rate control (PTESE) registers. Refer to Section 6.4, “Parallel
I/O Controls” for more information about general-purpose I/O control.
When the SCI1 module is enabled, PTE0 serves as the SCI1 module’s transmit pin (TxD1) and PTE1
serves as the receive pin (RxD1). Refer to Chapter 11, “Serial Communications Interface (SCI) Module”
for more information about using PTE0 and PTE1 as SCI pins.
When the SPI module is enabled, PTE2 serves as the SPI module’s slave select pin (SS1), PTE3 serves as
the master-in slave-out pin (MISO1), PTE4 serves as the master-out slave-in pin (MOSI1), and PTE5
serves as the SPI clock pin (SPSCK1). Refer to Chapter 12, “Serial Peripheral Interface (SPI) Module for
more information about using PTE5–PTE2 as SPI pins.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
81