MC9S08GB60 Datasheet, PDF (123/290 Pages) Motorola, Inc – Microcontrollers

ICG Registers and Control Bits
Bit 7
6
5
4
3
2
1
Bit 0
Read:
FLT
Write:
Reset: 1
1
0
0
0
0
0
0
Figure 7-18. ICG Lower Filter Register (ICGFLTL)
The filter registers show the filter value (FLT).
FLT — Filter Value
The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are
read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In
self-clocked mode, any write to ICGFLTU updates the current 12-bit filter value. Writes to the
ICGFLTU register will not affect FLT if a previous latch sequence is not complete.
7.5.6 ICG Trim Register (ICGTRM)
7
6
5
4
3
2
1
0
Read:
Write:
TRIM
POR: 1
0
0
0
0
0
0
0
Reset: U
U
U
U
U
U
U
U
U = Unaffected by MCU reset
Figure 7-19. ICG Trim Register (ICGTRM)
TRIM — ICG Trim Setting
The TRIM bits control the internal reference generator frequency. They allow a ± 25% adjustment of
the nominal (POR) period. The bit’s effect on period is binary weighted (i.e., bit 1 will adjust twice as
much as changing bit 0). Increasing the binary value in TRIM will increase the period and decreasing
the value will decrease the period.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
123