MC9S08GB60 Datasheet, PDF (142/290 Pages) Motorola, Inc – Microcontrollers

Central Processor Unit (CPU)
Table 8-1. HCS08 Instruction Set Summary (Sheet 7 of 7)
Source
Form
Operation
Description
Effect
on CCR
VH I NZC
SUB #opr8i
SUB opr8a
SUB opr16a
SUB oprx16,X
SUB oprx8,X
SUB ,X
SUB oprx16,SP
SUB oprx8,SP
Subtract
A ← (A) – (M)
PC ← (PC) + $0001
Push (PCL); SP ← (SP) – $0001
Push (PCH); SP ← (SP) – $0001
Push (X); SP ← (SP) – $0001
SWI
Software Interrupt
Push (A); SP ← (SP) – $0001
Push (CCR); SP ← (SP) – $0001
I ← 1;
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
Transfer Accumulator to
CCR
CCR ← (A)
TAX
Transfer Accumulator to
X (Index Register Low)
X ← (A)
TPA
Transfer CCR to
Accumulator
A ← (CCR)
TST opr8a
TSTA
TSTX
TST oprx8,X
TST ,X
TST oprx8,SP
Test for Negative or Zero
(M) – $00
(A) – $00
(X) – $00
(M) – $00
(M) – $00
(M) – $00
TSX
Transfer SP to Index Reg.
H:X ← (SP) + $0001
TXA
Transfer X (Index Reg.
Low) to Accumulator
A ← (X)
TXS
Transfer Index Reg. to SP
SP ← (H:X) – $0001
WAIT
Enable Interrupts; Wait
for Interrupt
I bit ← 0; Halt CPU
1 _{Bus clock frequency is one-half of the CPU clock frequency.}
IMM
DIR
EXT
––
IX2
IX1
IX
SP2
SP1
– – 1 – – – INH
INH
– – – – – – INH
– – – – – – INH
0––
DIR
INH
–
INH
IX1
IX
SP1
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – 0 – – – INH
A0 ii
2
B0 dd
3
C0 hh ll 4
D0 ee ff 4
E0 ff
3
F0
3
9ED0 ee ff 5
9EE0 ff
4
83
11
84
1
97
1
85
1
3D dd
4
4D
1
5D
1
6D ff
4
7D
3
9E6D ff
5
95
2
9F
1
94
2
8F
2+
MC9S08GB/GT Data Sheet, Rev. 2.3
142
Freescale Semiconductor