MC9S08GB60 Datasheet, PDF (120/290 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
LOCRE — Loss of Clock Reset Enable
The LOCRE bit determines how the system handles a loss of clock condition.
1 = Generate a reset request on loss of clock.
0 = Generate an interrupt request on loss of clock.
RFD — Reduced Frequency Divider
The RFD bits control the value of the divider following the clock select circuitry. The value specified
by the RFD bits establishes the division factor (R) applied to the selected output clock source. Writes
to the RFD bits will not take effect if a previous write is not complete.
Table 7-8. RFD Reduced Frequency Divider Select
RFD
000
001
010
011
100
101
110
111
Division Factor (R)
÷1
÷2
÷4
÷8
÷16
÷32
÷64
÷128
7.5.3
ICG Status Register 1 (ICGS1)
Read:
Write:
Reset:
Bit 7
6
CLKST
5
REFST
4
LOLS
0
0
0
0
= Unimplemented or Reserved
3
LOCK
0
2
LOCS
1
ERCS
0
0
Bit 0
ICGIF
1
0
Figure 7-15. ICG Status Register 1 (ICGS1)
CLKST — Clock Mode Status
The CLKST bits indicate the current clock mode. The CLKST bits don’t update immediately after a
write to the CLKS bits due to internal synchronization between clock domains.
MC9S08GB/GT Data Sheet, Rev. 2.3
120
Freescale Semiconductor