MC9S08GB60 Datasheet, PDF (122/290 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
ICGIF — ICG Interrupt Flag
The ICGIF read/write flag is set when an ICG interrupt request is pending. It is cleared by a reset or
by reading the ICG status register when ICGIF is set and then writing a 1 to ICGIF. If another ICG
interrupt occurs before the clearing sequence is complete, the sequence is reset so ICGIF would remain
set after the clear sequence was completed for the earlier interrupt. Writing a 0 to ICGIF has no effect.
1 = An ICG interrupt request is pending.
0 = No ICG interrupt request is pending.
7.5.4 ICG Status Register 2 (ICGS2)
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
0
DCOS
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-16. ICG Status Register 2 (ICGS2)
DCOS — DCO Clock Stable
The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error has not
changed by more than n_unlock for two consecutive samples and the DCO clock is not static. This bit is
used when exiting off state if CLKS = X1 to determine when to switch to the requested clock mode. It
is also used in self-clocked mode to determine when to start monitoring the DCO clock. This bit is
cleared upon entering the off state.
1 = DCO clock is stable.
0 = DCO clock is unstable.
7.5.5 ICG Filter Registers (ICGFLTU, ICGFLTL)
Bit 15
14
13
12
11
10
9
Bit 8
Read: 0
0
0
0
FLT
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-17. ICG Upper Filter Register (ICGFLTU)
MC9S08GB/GT Data Sheet, Rev. 2.3
122
Freescale Semiconductor