MC9S08GB60 Datasheet, PDF (230/290 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ATD) Module
14.6.1 ATD Control (ATDC)
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ATDPU DJM RES8 SGN
PRS
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 14-5. ATD Control Register (ATD1C)
Writes to the ATD control register will abort the current conversion, but will not start a new conversion.
ATDPU — ATD Power Up
This bit provides program on/off control over the ATD, reducing power consumption when the ATD
is not being used. When cleared, the ATDPU bit aborts any conversion in progress.
1 = ATD functionality.
0 = Disable the ATD and enter a low-power state.
DJM — Data Justification Mode
This bit determines how the 10-bit conversion result data maps onto the ATD result register bits. When
RES8 is set, bit DJM has no effect and the 8-bit result is always located in ATD1RH.
For left-justified mode, result data bits 9–2 map onto bits 7–0 of ATD1RH, result data bits 1 and 0 map
onto ATD1RL bits 7 and 6, where bit 7 of ATD1RH is the most significant bit (MSB).
76543210
76543210
9
RESULT
0
ATD1RH
ATD1RL
Figure 14-6. Left-Justified Mode
For right-justified mode, result data bits 9 and 8 map onto bits 1 and 0 of ATD1RH, result data bits
7–0 map onto ATD1RL bits 7–0, where bit 1 of ATD1RH is the most significant bit (MSB).
76543210
76543210
9
RESULT
0
ATD1RH
ATD1RL
Figure 14-7. Right-Justified Mode
The effect of the DJM bit on the result is shown in Table 14-3.
1 = Result register data is right justified.
0 = Result register data is left justified.
MC9S08GB/GT Data Sheet, Rev. 2.3
230
Freescale Semiconductor