MC9S08GB60 Datasheet, PDF (72/290 Pages) Motorola, Inc – Microcontrollers

Chapter 5 Resets, Interrupts, and System Configuration
COPE — COP Watchdog Enable
This write-once bit defaults to 1 after reset.
1 = COP watchdog timer enabled (force reset on timeout).
0 = COP watchdog timer disabled.
COPT — COP Watchdog Timeout
This write-once bit defaults to 1 after reset.
1 = Long timeout period selected (2¹⁸ cycles of BUSCLK).
0 = Short timeout period selected (2¹³ cycles of BUSCLK).
STOPE — Stop Mode Enable
This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is disabled and a
user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
1 = Stop mode enabled.
0 = Stop mode disabled.
BKGDPE — Background Debug Mode Pin Enable
The BKGDPE bit enables the PTG0/BKGD/MS pin to function as BKGD/MS. When the bit is clear,
the pin will function as PTG0, which is an output-only general-purpose I/O. This pin always defaults
to BKGD/MS function after any reset.
1 = BKGD pin enabled.
0 = BKGD pin disabled.
5.8.5 System Device Identification Register (SDIDH, SDIDL)
This read-only register is included so host development systems can identify the HCS08 derivative and
revision number. This allows the development software to recognize where specific memory blocks,
registers, and control bits are located in a target MCU.
Bit 7
6
5
4
3
2
1
Bit 0
Read: REV3
REV2
REV1 REV0 ID11
ID10
ID9
ID8
Reset: 0¹
0⁽¹⁾
0⁽¹⁾
0⁽¹⁾
0
0
0
0
Read: ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Reset: 0
0
0
0
0
0
1
0
= Unimplemented or Reserved
1 _{The revision number that is hard coded into these bits reflects the current silicon revision level.}
Figure 5-6. System Device Identification Register (SDIDH, SDIDL)
REV[3:0] — Revision Number
The high-order 4 bits of address $1806 are hard coded to reflect the current mask set revision number
(0–F).
MC9S08GB/GT Data Sheet, Rev. 2.3
72
Freescale Semiconductor