MC9S08GB60 Datasheet, PDF (140/290 Pages) Motorola, Inc – Microcontrollers

Central Processor Unit (CPU)
Table 8-1. HCS08 Instruction Set Summary (Sheet 5 of 7)
Source
Form
Operation
Description
Effect
on CCR
VH I NZC
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
LDA oprx16,SP
LDA oprx8,SP
LDHX #opr16i
LDHX opr8a
LDHX opr16a
LDHX ,X
LDHX oprx16,X
LDHX oprx8,X
LDHX oprx8,SP
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
MUL
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
NOP
NSA
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
ORA oprx16,SP
ORA oprx8,SP
PSHA
PSHH
PSHX
Load Accumulator from
Memory
Load Index Register (H:X)
from Memory
Load X (Index Register
Low) from Memory
Logical Shift Left
(Same as ASL)
Logical Shift Right
Move
Unsigned multiply
Negate
(Two’s Complement)
No Operation
Nibble Swap
Accumulator
Inclusive OR Accumulator
and Memory
Push Accumulator onto
Stack
Push H (Index Register
High) onto Stack
Push X (Index Register
Low) onto Stack
A ← (M)
H:X ← (M:M + $0001)
X ← (M)
C
b7
0
b0
0
b7
C
b0
(M)_destination ← (M)_source
H:X ← (H:X) + $0001 in
IX+/DIR and DIR/IX+ Modes
X:A ← (X) × (A)
M ← – (M) = $00 – (M)
A ← – (A) = $00 – (A)
X ← – (X) = $00 – (X)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
Uses 1 Bus Cycle
A ← (A[3:0]:A[7:4])
A ← (A) | (M)
Push (A); SP ← (SP) – $0001
Push (H); SP ← (SP) – $0001
Push (X); SP ← (SP) – $0001
0––
IMM
DIR
EXT
–
IX2
IX1
IX
SP2
SP1
A6 ii
2
B6 dd
3
C6 hh ll 4
D6 ee ff 4
E6 ff
3
F6
3
9ED6 ee ff 5
9EE6 ff
4
0––
IMM
DIR
EXT
– IX
IX2
IX1
SP1
45 jj kk 3
55 dd
4
32 hh ll 5
9EAE
5
9EBE ee ff 6
9ECE ff
5
9EFE ff
5
0––
IMM
DIR
EXT
–
IX2
IX1
IX
SP2
SP1
AE ii
2
BE dd
3
CE hh ll 4
DE ee ff 4
EE ff
3
FE
3
9EDE ee ff 5
9EEE ff
4
––
DIR
38 dd
5
INH
48
1
INH
58
1
IX1
68 ff
5
IX
78
4
SP1
9E68 ff
6
DIR
34 dd
5
INH
44
1
––0
INH
IX1
54
1
64 ff
5
IX
74
4
SP1
9E64 ff
6
0––
DIR/DIR
–
DIR/IX+
IMM/DIR
IX+/DIR
4E dd dd 5
5E dd
5
6E ii dd 4
7E dd
5
– 0 – – – 0 INH
42
5
––
DIR
30 dd
5
INH
40
1
INH
50
1
IX1
60 ff
5
IX
70
4
SP1
9E60 ff
6
– – – – – – INH
9D
1
– – – – – – INH
62
1
0––
IMM
DIR
EXT
–
IX2
IX1
IX
SP2
SP1
AA ii
2
BA dd
3
CA hh ll 4
DA ee ff 4
EA ff
3
FA
3
9EDA ee ff 5
9EEA ff
4
– – – – – – INH
87
2
– – – – – – INH
8B
2
– – – – – – INH
89
2
MC9S08GB/GT Data Sheet, Rev. 2.3
140
Freescale Semiconductor