MC9S08GB60 Datasheet, PDF (215/290 Pages) Motorola, Inc – Microcontrollers

13.5.3 IIC Control Register (IIC1C)
Inter-Integrated Circuit (IIC) Module
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
IICEN IICIE MST
TX
TXAK
Write:
RSTA
Reset: 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-7. IIC Control Register (IIC1C)
IICEN — IIC Enable
The IICEN bit determines whether the IIC module is enabled.
1 = IIC is enabled.
0 = IIC is not enabled.
IICIE — IIC Interrupt Enable
The IICIE bit determines whether an IIC interrupt is requested.
1 = IIC interrupt request enabled.
0 = IIC interrupt request not enabled.
MST — Master Mode Select
The MST bit is changed from a 0 to a 1 when a START signal is generated on the bus and master mode
is selected. When this bit changes from a 1 to a 0 a STOP signal is generated and the mode of operation
changes from master to slave.
1 = Master Mode.
0 = Slave Mode.
TX — Transmit Mode Select
The TX bit selects the direction of master and slave transfers. In master mode this bit should be set
according to the type of transfer required. Therefore, for address cycles, this bit will always be high.
When addressed as a slave this bit should be set by software according to the SRW bit in the status
register.
1 = Transmit.
0 = Receive.
TXAK — Transmit Acknowledge Enable
This bit specifies the value driven onto the SDA during data acknowledge cycles for both master and
slave receivers.
1 = No acknowledge signal response is sent.
0 = An acknowledge signal will be sent out to the bus after receiving one data byte.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
215