MC9S12E128CFUE Datasheet, PDF (91/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 2 128 Kbyte Flash Module (FTS128K1V1)
2.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Module Base + 0x0000
R
W
Reset
7
FDIVLD
0
6
PRDIV8
5
FDIV5
4
FDIV4
3
FDIV3
2
FDIV2
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-4. Flash Clock Divider Register (FCLKDIV)
1
FDIV1
0
0
FDIV0
0
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
Table 2-3. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
6
PRDIV8
5–0
FDIV[5:0]
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written to since the last reset
Enable Prescalar by 8
0 The oscillator clock is directly fed into the Flash clock divider
1 The oscillator clock is divided by 8 before feeding into the Flash clock divider
Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Refer to Section 2.4.1.1, “Writing the
FCLKDIV Register” for more information.
2.3.2.2 Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
Module Base + 0x0001
R
W
Reset
7
KEYEN1
F
6
KEYEN0
5
NV5
4
NV4
3
NV3
2
NV2
F
F
F
F
F
= Unimplemented or Reserved
Figure 2-5. Flash Security Register (FSEC)
1
SEC1
F
0
SEC0
F
All bits in the FSEC register are readable but not writable.
The FSEC register is loaded from the Flash configuration field at 0xFF0F during the reset sequence,
indicated by F in Figure 2-5.
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
91