MC9S12E128CFUE Datasheet, PDF (358/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
ALIGNMENT REFERENCE
UP COUNTER
MODULUS = 4
PWM OUTPUT
DUTY CYCLE = 50%
Figure 11-42. Edge-Aligned PWM Output
NOTE
Because of the equals-comparator architecture of this PMF, the modulus
equals zero case is considered illegal. Therefore, the modulus register does
not return to zero, and a modulus value of zero will result in waveforms
inconsistent with the other modulus waveforms. If a modulus of zero is
loaded, the counter will continually count down from $7FFF. This operation
will not be tested or guaranteed. Consider it illegal. However, the dead-time
constraints and fault conditions will still be guaranteed.
11.4.3.2 Period
A PWM period is determined by the value written to the PWM counter modulo register.
The PWM counter is an up/down counter in a center-aligned operation. In this mode the PWM highest
output resolution is two bus clock cycles.
PWM period = (PWM modulus) × (PWM clock period) × 2
COUNT
12343210
UP/DOWN COUNTER
MODULUS = 4
PWM CLOCK PERIOD
PWM PERIOD = 8 x PWM CLOCK PERIOD
Figure 11-43. Center-Aligned PWM Period
MC9S12E128 Data Sheet, Rev. 1.07
358
Freescale Semiconductor