MC9S12E128CFUE Datasheet, PDF (379/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
FAULT0 OR
FAULT2
PWMS ENABLED PWMS DISABLED
PWMS ENABLED
FFLAGx
CLEARED
Figure 11-78. Manual Fault Clearing (Faults 0 & 2) - QSMP=01, 10, or 11
FAULT1 OR
FAULT3
PWMS ENABLED
PWMS DISABLED
PWMS ENABLED
FFLAGx
CLEARED
Figure 11-79. Manual Fault Clearing (Faults 1 & 3)
NOTE
PWM half-cycle boundaries occur at both the PWM cycle start and when the
counter equals the modulus, so in edge-aligned operation full-cycles and
half-cycles are equal.
NOTE
Fault protection also applies during software output control when the
OUTCTLx bits are set. Fault clearing still occurs at half PWM cycle
boundaries while the PWM generator is engaged, PWMEN equals one. But
the OUTx bits can control the PWM pins while the PWM generator is off,
PWMEN equals zero. Thus, fault clearing occurs at IPbus cycles while the
PWM generator is off and at the start of PWM cycles when the generator is
engaged.
11.5 Resets
All PWM registers are reset to their default values upon any system reset.
11.6 Clocks
The system bus clock is the only clock required by this module.
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
379