MC9S12E128CFUE Datasheet, PDF (241/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 7 Digital-to-Analog Converter (DAC8B1CV1)
7.3.2.2 Reserved Register (DACC1)
This register is reserved.
Module Base + 0x0000
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-4. Reserved Register (DACC1)
Read: always read $00
Write: unimplemented
7.3.2.3 DAC Data Register — Left Justified (DACD)
Module Base + 0x0002
R
W
Reset
7
BIT 7
0
6
BIT 6
5
BIT 5
4
BIT 4
3
BIT 3
2
BIT 2
0
0
0
0
0
Figure 7-5. DAC Data Register — Left Justified (DACD)
1
BIT 1
0
0
BIT 0
0
Read: read zeroes when DJM is set
Write: unimplemented when DJM is set
The DAC data register is an 8-bit readable/writable register that stores the data to be converted when DJM
bit is clear. When the DACE bit is set, the value in this register is converted into an analog voltage such
that values from $00 to $FF result in equal voltage increments from V_SSA to V_REF. When DJM bit is set,
this register reads zeroes and cannot be written.
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
241