MC9S12E128CFUE Datasheet, PDF (302/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 10 Inter-Integrated Circuit (IICV2)
10.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
Table 10-1. IIC Register Summary
Register
Name
IBAD
IBFD
IBCR
IBSR
IBDR
Bit 7
R
ADR7
W
R
IBC7
W
R
IBEN
W
R TCF
W
R
D7
W
6
ADR6
5
ADR5
4
ADR4
IBC6
IBC5
IBC4
IBIE
MS/SL
Tx/Rx
IAAS
IBB
IBAL
D6
D5
D4
= Unimplemented or Reserved
3
ADR3
IBC3
TXAK
0
D3
2
ADR2
IBC2
0
RSTA
SRW
D2
1
ADR1
Bit 0
0
IBC1
IBC0
0
IBSWAI
RXAK
IBIF
D1
D0
10.3.2.1 IIC Address Register (IBAD)
7
6
5
4
3
2
1
0
R
0
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-2. IIC Bus Address Register (IBAD)
Read and write anytime
This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
Table 10-2. IBAD Field Descriptions
Field
Description
7:1
ADR[7:1]
0
Reserved
Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default
mode of IIC bus is slave mode for an address match on the bus.
Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
MC9S12E128 Data Sheet, Rev. 1.07
302
Freescale Semiconductor